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wireless power receiver for 15w applications p9221 - r datasheet ? 2017 integrated device technology, inc . 1 april 4 , 2017 description the p9221 - r is a high efficiency, qi - compliant wireless power receiver target ed for applications up to 15w . using magnetic inductive charging technology, the receiver converts an ac power signal from a resonant tank into a regulated dc output voltage setting with 9v and 12v . the integrated , low rds (on) syn - chronous rectifier and ultra - low dropout offer high eff iciency making the pro duct ideally suited for battery - operated applications. the p9221 - r includes an industry - leading 32 bit arm? cortex? - m0 processor offering a high level of programmability . in addition, the device features proprietary alignment guide in formation for optimum coupling between the receiver and the transmitter, a programmable current limit , and a patent ed over - volt age pro tection scheme eliminating the need for additional capacitors generally used by the receivers , minimizing the external co mponent count and cost . together with the p9242 - r transmitter (t x ) , the p9221 - r is a complete wireless power system solution for power applications up to 15w . the p9221 - r is available in a 52 - wlcsp package and it is rated for a 0 to 85c ambient operating temperature range. typical applications ? fast charge cellphone ? tablets ? accessories ? medical feature s ? single - c hip s olution supporting up to 15w applications ? wpc - 1.2. 3 compliant ? patented over - voltage protection clamp eliminating external capacitors ? 87% peak dc - to - dc efficiency with p9242 - r t x ? proprietary coil alignment guide ? full synchronous rectifier with low rds(on) s witches ? programmable output voltage: 9v and 12v ? embedded 32 - bit arm? cortex? - m0 processor ? dedicated remote temperature sensing ? power transfer led indicator ? programmable current limit ? active - low enable pin for electrical on/off ? open - drain interrupt flag ? supports i 2 c interface ? 0 to +85c ambient operating temperature range ? 52 - wlcsp ( 2.64 ? 3.94 mm ; 0.4mm pitch) typical application circuit a c 1 c o m m 1 b s t 1 a c 2 c o m m 2 b s t 2 v r e c t o u t v s e t i l i m r p p o r p p g s d a s c l i n t v d d 5 v g n d p r o g r a m m i n g r e s i s t o r s l s p 9 2 2 1 - r t h m a l i g n x a l i g n y v d d 1 8 c s c o u t
p9221 - r datasheet ? 2017 integrated device technology, inc . 2 april 4 , 2017 contents 1. pin assignments ................................ ................................ ................................ ................................ ................................ ........................... 5 2. pin descriptions ................................ ................................ ................................ ................................ ................................ ............................ 5 3. absolute maximum ratings ................................ ................................ ................................ ................................ ................................ .......... 8 4. thermal characteristic s ................................ ................................ ................................ ................................ ................................ ................ 9 5. electrical characteristics ................................ ................................ ................................ ................................ ................................ .............. 9 6. typical performance characteristics ................................ ................................ ................................ ................................ .......................... 12 7. function block diagram ................................ ................................ ................................ ................................ ................................ ............. 15 8. theory of operation ................................ ................................ ................................ ................................ ................................ .................... 16 8.1 ldo C low dropout regulators ................................ ................................ ................................ ................................ ....................... 16 8.2 setting the output voltage C voset ................................ ................................ ................................ ................................ ............... 16 8.3 sink pin ................................ ................................ ................................ ................................ ................................ .......................... 17 8.4 rectifier voltage C vrect ................................ ................................ ................................ ................................ ............................... 17 8.5 over - current limit C ilim ................................ ................................ ................................ ................................ ................................ . 17 8.6 interrupt function C int ................................ ................................ ................................ ................................ ................................ ... 17 8.7 enable pin C en ................................ ................................ ................................ ................................ ................................ ............... 17 8.8 thermal protection ................................ ................................ ................................ ................................ ................................ ........... 17 8.9 external temperature sensing C ts ................................ ................................ ................................ ................................ ................ 17 8.10 alignment guide C alignx and aligny ................................ ................................ ................................ ................................ ........ 18 8.11 received power packet offset and gain calibration C rppo and rppg ................................ ................................ ...................... 18 8.12 advanced foreign object detection (fod) ................................ ................................ ................................ ................................ ..... 18 9. communication interface ................................ ................................ ................................ ................................ ................................ ............ 20 9.1 modulation/communication ................................ ................................ ................................ ................................ .............................. 20 9.2 bit encoding scheme for ask ................................ ................................ ................................ ................................ ......................... 21 9.3 byte encoding for ask ................................ ................................ ................................ ................................ ................................ ..... 21 9.4 packet structure ................................ ................................ ................................ ................................ ................................ .............. 21 10. wpc mode characteristics ................................ ................................ ................................ ................................ ................................ ........ 22 10.1 selection phase or startup ................................ ................................ ................................ ................................ .............................. 22 10.2 ping phase (digital ping) ................................ ................................ ................................ ................................ ................................ . 22 10.3 identification and configuration phase ................................ ................................ ................................ ................................ ............ 23 10.4 negotiation phase ................................ ................................ ................................ ................................ ................................ ............ 23 10.5 calibration phase ................................ ................................ ................................ ................................ ................................ ............. 23 10.6 power transfer phase ................................ ................................ ................................ ................................ ................................ ..... 23 11. functional registers ................................ ................................ ................................ ................................ ................................ ................... 24 12. application information ................................ ................................ ................................ ................................ ................................ ............... 29 12.1 power dissipation and thermal requirements ................................ ................................ ................................ ................................ 29 12.2 recommended coils ................................ ................................ ................................ ................................ ................................ ........ 29 12.3 typical application schematic ................................ ................................ ................................ ................................ ......................... 30 12.4 bill of materials (bom) ................................ ................................ ................................ ................................ ................................ ..... 31
p9221 - r datasheet ? 2017 integrated device technology, inc . 3 april 4 , 2017 13. package drawings ................................ ................................ ................................ ................................ ................................ ...................... 32 14. recommended land pattern ................................ ................................ ................................ ................................ ................................ ...... 33 15. special notes: ahg52 wlcsp - 52 package assembly ................................ ................................ ................................ ............................. 34 16. marking diagram ................................ ................................ ................................ ................................ ................................ ........................ 34 17. ordering information ................................ ................................ ................................ ................................ ................................ ................... 34 18. revision history ................................ ................................ ................................ ................................ ................................ .......................... 35 list of figures figu re 1. pin assignments ................................ ................................ ................................ ................................ ................................ .................. 5 figure 2. efficiency vs. output load: v out = 12v ................................ ................................ ................................ ................................ ............. 12 figure 3. load reg. vs. output load: v out = 12v ................................ ................................ ................................ ................................ ............ 12 figu re 4. efficiency vs. output load: v out = 9v ................................ ................................ ................................ ................................ ............... 12 figure 5. load reg. vs. output load: v out = 9v ................................ ................................ ................................ ................................ .............. 12 figure 6. efficiency vs. output load: v out = 5v ................................ ................................ ................................ ................................ ............... 12 figure 7. load reg. vs. output load: v out = 5v ................................ ................................ ................................ ................................ .............. 12 figure 8. rectifier voltage vs. load: v out = 12v ................................ ................................ ................................ ................................ .............. 13 figu re 9. rectifier voltage vs. load: v out = 9v ................................ ................................ ................................ ................................ ................ 13 figure 10. rectifier voltage vs. load: v out = 5v ................................ ................................ ................................ ................................ ................ 13 figure 11. current limit vs. v ilim ................................ ................................ ................................ ................................ ................................ ........ 13 figure 12. x and y misalignment ................................ ................................ ................................ ................................ ................................ ........ 13 figure 13. max. power vs. misalignment: v out =12v ................................ ................................ ................................ ................................ .......... 13 figure 14. enable startup: v out = 12v; i out = 1.2a ................................ ................................ ................................ ................................ ............ 14 figure 15. transient resp: v out = 12v; i out = 0 to 1.2a ................................ ................................ ................................ ................................ .... 14 figure 16. transient resp: v out = 12v; i out = 1.3a to 0 ................................ ................................ ................................ ................................ .... 14 figure 17. functional block diagram ................................ ................................ ................................ ................................ ................................ .. 15 figure 18. exampl e of differential bi - phase decoding for fsk ................................ ................................ ................................ .......................... 20 figure 19. example of asynchronous serial byte format for fsk ................................ ................................ ................................ ..................... 20 figure 20. bit encoding scheme ................................ ................................ ................................ ................................ ................................ ........ 21 figure 21. byte encoding scheme ................................ ................................ ................................ ................................ ................................ ..... 21 figure 22. communicat ion packet structure ................................ ................................ ................................ ................................ ...................... 21 figure 23. wpc power transfer phases flowchart ................................ ................................ ................................ ................................ ........... 22 figure 24. p9221 - r typical application schematic ................................ ................................ ................................ ................................ ............ 30 figure 25. package outline drawing ................................ ................................ ................................ ................................ ................................ .. 32 figure 26. ahg52 52 - wlcsp land pattern ................................ ................................ ................................ ................................ ...................... 33
p9221 - r datasheet ? 2017 integrated device technology, inc . 4 april 4 , 2017 list of tables table 1. pin descriptions ................................ ................................ ................................ ................................ ................................ ................... 5 table 2. absolute maximum ratings ................................ ................................ ................................ ................................ ................................ . 8 table 3. esd information ................................ ................................ ................................ ................................ ................................ .................. 8 table 4. package thermal info rmation ................................ ................................ ................................ ................................ ............................. 9 table 5. electrical characteristics ................................ ................................ ................................ ................................ ................................ ..... 9 table 6. setting the output voltage ................................ ................................ ................................ ................................ ................................ 16 table 7. maximum estimated power loss ................................ ................................ ................................ ................................ ...................... 19 table 8. device identification register ................................ ................................ ................................ ................................ ............................ 24 table 9. firmware major revision ................................ ................................ ................................ ................................ ................................ ... 24 table 10. firmware minor revi sion ................................ ................................ ................................ ................................ ................................ ... 24 table 11. status registers ................................ ................................ ................................ ................................ ................................ ................ 24 table 12. interrupt status registers ................................ ................................ ................................ ................................ ................................ .. 25 table 13. interru pt enable registers ................................ ................................ ................................ ................................ ................................ . 25 table 14. battery charge status ................................ ................................ ................................ ................................ ................................ ....... 25 table 15. end power transfer ................................ ................................ ................................ ................................ ................................ ........... 26 table 16. read register C output voltage ................................ ................................ ................................ ................................ ........................ 26 table 17. read register C vrect voltage ................................ ................................ ................................ ................................ ...................... 26 table 18. read register C iout current ................................ ................................ ................................ ................................ .......................... 26 table 19. read register C die temperature ................................ ................................ ................................ ................................ ..................... 27 table 20. read register C operating frequency ................................ ................................ ................................ ................................ .............. 27 table 21. alignment x value register ................................ ................................ ................................ ................................ ............................... 27 table 22. alignme nt y value register ................................ ................................ ................................ ................................ ............................... 27 table 23. command register ................................ ................................ ................................ ................................ ................................ ............ 28 table 24. recommended coil manufacturers ................................ ................................ ................................ ................................ ................... 29 table 25. p9221 - r mm evaluation kit v2.1 bill of materials ................................ ................................ ................................ ............................. 31
p9221 - r datasheet ? 2017 integrated device technology, inc . 5 april 4 , 2017 1. pin assignments figure 1 . pin assignments 2. pin descriptions table 1 . pin descriptions pins name type function a1 comm1 o open - drain output used to communicate wit h the transmitter. connect a 47 nf capacitor from ac1 to comm1. a2 alignx i ac input for coil alignment guide . if not use d , connect to gnd through a 10 k ? resistor. a3 scl i i 2 c clock pin. open - drain output. connect a 5. 1 k ? resistor to vdd18 pin . a4 voset i programming pin for setting the output voltage. connect this pin to the center tap of a resistor divider to set the output voltage. for more information, refer to section 8.2 for different output voltage settings. c o m m 1 r s v 4 g n d o u t a l i g n x a l i g n y s i n k o u t s c l s d a i n t o u t v o s e t i l i m r p p o o u t r p p g d e n o u t c o m m 2 r s v 5 g n d o u t a b c d e f 1 2 3 4 5 6 a c 1 r s v 3 t s a c 2 b s t 2 g b s t 1 a c 1 r s v 2 r s v 1 a c 2 a c 2 h a c 1 g n d g n d g n d g n d g n d g n d j b o t t o m v i e w e n v d d 1 8 v d d 5 v v r e c t v r e c t v r e c t v r e c t v r e c t v r e c t v r e c t v r e c t
p9221 - r datasheet ? 2017 integrated device technology, inc . 6 april 4 , 2017 pins name type function a5 rppg i received p ower p acket gain (rppg) calibration pin for f oreign o bject d etection ( fod ) t uning. connect this pin to the center tap of a resistor divider to set the gain of the fod. the fod is disabled by connecting the center tap of two 10k resistors to vdd18 pin and gnd . a6 comm2 o open - drain output used to communicate wit h the transmitter. connect a 47 nf capacitor from ac2 to comm2. b1 rsv 4 reserved for internal use. do not connect. b2 aligny i ac input for coil alignment guide . if not use d , connect to gnd through a 10k? resistor. b3 sda i/o i 2 c data pin. open - drain output. connect a 5. 1 k resistor to vdd18 pin . b4 ilim i programmable over - current limit pin. connect this pin to the center tap of a resistor divider to set the current limit. for more information about the current limit function , see section 8.5 . b5 en ? ? ? ? i active - low enable pin. pulling this pin to logic high forces the device into s hut d own m ode. when connected to logic low, the device is enabled. do not leave this pin floating. b6 rsv5 reserved for internal use. do not connect. c1, c6, j1, j2, j3,j4,j5,j6 gnd gnd ground. c2 sink o open - drain output for controlling the rectifier clamp. connect a 36? resistor from this pin to the vrect pin. c3 int ? ? ? ? o interrupt flag pin. this is an open - drain output that signals fault interrupts. it is pulled low if any of these faults exists: an over - voltage is detected, an over - current condition is detected, the die temperature exceeds 140c, or an external over - tempe rature condition is detected on the ts pin. it is also asserted low when en is high. c onnect to vdd18 through a 10k ? resistor. see section 8.6 for additional conditions affecting the interrupt flag. c4 rppo o received power packet offset (rppo) calibration pin for fod tuning. connect to the center tap of the resistor divider to set the offset of the fod. the fod is disabled by connecting the center tap of two 10k resistors to vdd18 pin and gnd. c5 den i reserved. must connect a 10k resistor to the vdd18 pin. d1, d2, d3, d4, d5, d6 out o regulated output voltage pin. connect three 10f capacitors from this pin to gnd. the default voltage is set to 12v when the voset pin is pulled up to vdd18 pin through a 10k resister. for more information about voset, see section 8.2 . e1, e2, e5, e6 f2, f3, f4, f5 vrect o output voltage of the synchronous rectifier bridge. connect three 10f capacitors from this pin to gnd. the rectifier voltage dynamically changes as the load changes . for more information, see the typical waveforms in section 6 . f1 vdd5v o internal 5v regulator output voltage for internal use. connect a 1 f capacitor from this pin to ground. do not load the pin. f6 vdd18 o internal 1.8v regulator output voltage. connect a 1 f capacitor from this pin to ground. do not load the pin. g1 bst1 o boost capacitor for driving the high - side switch of the internal rectifier. connect a 15nf capacitor from the ac1 pin to bst1. g2, h1, h2, ac1 i ac input power. connect to th e resonant capacitor (c s ). g3 rsv3 i reserved pins. must be connected to gnd.
p9221 - r datasheet ? 2017 integrated device technology, inc . 7 april 4 , 2017 pins name type function g4 rsv1 reserved for internal use. do not connect. g5, h5, h6 ac2 i ac input power. connect to the rx coil (l s ). g6 bst2 o boost capacitor for driving the high - side switch of the internal rectifier. connect a 15nf capacitor from the ac2 pin to bst2. h3 rsv2 reserved pins. must be connected to gnd. h4 ts i remote temperature sensor for over - temperature shutdown. connect to the ntc thermistor network. if not used, c onnect to vdd18 pin through the 10k resistor.
p9221 - r datasheet ? 2017 integrated device technology, inc . 8 april 4 , 2017 3. absolute maximum ratings stresses greater than those listed as absolute maximum ratings in table 2 could cause permanent damage to the device. th ese are stress rating s only , and functional operation of the device at these or any other conditions above those indicated in the operational sec tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods m ight affect reliability. table 2 . absolute maximum ratings pin s [ a ] ratin g [ b ] units ac 1 [c] , ac 2 [c] , comm1, comm2 - 0.3 to 20 v en ? ? ? ? - 0.3 to 28 v sink , vrect - 0.3 to 24 v den , ilim, rppg , rppo, vdd18, voset - 0.3 to 2 v alignx, aligny, int ? ? ? ? , scl, sda, ts, vdd5v - 0.3 to 6 v bst1, bst2 - 0.3 to ac1+6, ac2+6 v out - 0.3 to 14.4 v maximum current on sink 1 a maximum rms current on comm1, comm2 500 ma maximum rms current from ac1, ac2 2 a [a] absolute m aximum r atings are not provided for reserved pins (rsv1, rsv2, rsv3, rsv4, rsv5, and den) . these pins are not used in the application. [b] all voltages are referred to ground unless otherwise noted. [c] during synchronous rectifier dead time, the voltage on the ac1 and ac2 pins is developed by current across the power fets body diodes , and it m ight be lower than - 0.3 v. this is a normal behavior and does not negatively impact the functionality or reliability of the product. table 3 . esd information test model pins ratings units hbm all pins except rsv2 and rsv3 2 kv rsv2, rsv3 pins 1 kv cdm all pins 500 v
p9221 - r datasheet ? 2017 integrated device technology, inc . 9 april 4 , 2017 4. thermal characteristics table 4 . package thermal information note: this thermal rating was calculated on a jedec 51 standard 4 - layer board with dimensions 76.2 x 114.3 mm in still air conditions. symbol description wlcsp rating 8 thermal balls units ja thermal resistance junction to ambien t [a] 47 ? c/w jc thermal resistance junction to case 0.202 ? c/w jb thermal resistance junction to board 4.36 ? c/w t j operating junction temperature [a] - 5 to +125 ? c t a ambient operating temperatur e [a] 0 to +85 ? c t stg storage temperature - 55 to +150 ? c t bump maximum soldering temperature (reflow, pb - free) 260 ? c [a] the maximum power dissipation is p d(max) = (t j(max) - t a ) / ja where t j(max) is 125c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. 5. electrical characteristics table 5 . electrical characteristics note: vrect = 5.5 v; c out = 4.7 f, en ? ? ? ? = low, unless otherwise noted. t j = 0 ? c to 125 ? c ; t ypical values are at 25c. symbol description conditions min typical max units under - voltage lock - out (uvlo) v uvlo_rising uvlo rising rising voltage on vrect 2.9 2.98 v v uvlo_hys uvlo hysteresis vrect falling 200 mv over - voltage protection v ovp - dc dc over - v oltage protection rising voltage 13.5 v v ovp - hys over - v oltage hysteresis 1 v quiescent current i active_suply supply current en = low, no load; vrect = 12.3v 3.0 ma i shd shut down mode current en = high; vrect = 12.3v 500 a v dd18 voltage v vdd18 vdd18 pin output voltag e [a] i vdd18 = 10 ma, c vdd18 = 1f 1.62 1.8 1.98 v
p9221 - r datasheet ? 2017 integrated device technology, inc . 10 april 4 , 2017 symbol description conditions min typical max units v dd5v voltage v vdd 5v vdd5v pin output voltag e [a] i vdd5v = 10ma, c vdd5v = 1f 4.5 5 5.5 v low drop - out (ldo) regulator i out_max maximum output current 1.25 a v out_12v 12v output voltage voset > 1.5v, vrect=12.3v 12 v v out_9v 9v output voltage 0.7v < voset < 1.2v, vrect=9.3v 9 v analog to digital converter n resolution 12 bit f sample sampling rate 67.5 ksa/s channel number of channels 8 v in,fs full - scale input voltage 2.1 v en ? ? ? ? pin v ih input threshold high 1.4 v v il input threshold low 0.25 v i il input current low v en = 0 v - 1 1 a i ih input current high v en = 5 v 2.5 a voset, ilim, ts, rppo, rppg i il input current l ow v voset , v ilim , v ts , v rppo , v rppg = 0 v - 1 1 a i ih input current h igh v voset , v ilim , v ts , v rppo , v rppg = 1.8 v - 1 1 a alignx, aligny and int ? ? ? ? pins i lkg input leakage current v alignx , v aligny , v int = 0v and 5 v - 1 1 a v ol outpu t logic l ow i ol = 8 ma 0.36 v i 2 c interface C scl, sda v il input threshold low 0.7 v v ih input threshold high 1.4 v i lkg input leakage current v scl , v sda = 0v and 5 v - 1 1 a v ol output logic low i ol = 8 ma 0.36 v f scl clock frequency 400 khz t hd,sta hold time (repeated) for start condition 0.6 s t hd : dat data hold time 0 ns t low clock low period 1.3 s t high clock high period 0.6 s
p9221 - r datasheet ? 2017 integrated device technology, inc . 11 april 4 , 2017 symbol description conditions min typical max units t su : sta set - up time for repeated start condition 0.6 s t buf bus free time between stop and start condition 1.3 s c b capacitive load for e ach bus line 150 pf c i scl, sda input capacitance 5 pf thermal shutdown t sd thermal s hutdown risin g [b] 140 c falling 120 c [a] do not externally load. for internal biasing only. [b] if th e die temperature exceeds 130c, the thermal_shtdn_status flag is set and an end power transfer ( ept ) packet is sent (see table 11 ) .
p9221 - r datasheet ? 2017 integrated device technology, inc . 12 april 4 , 2017 6. typical performance characteristics the following p erformance characteristics were taken using a p9242 - r, 15 w wireless power transmitter at t a = 25c unless otherwise noted. figure 2 . efficiency vs. output load : v out = 12v figure 3 . load reg. vs. output lo ad : v out = 12v figure 4 . efficiency vs. output load : v out = 9v figure 5 . load reg. vs. output load : v out = 9v figure 6 . efficiency vs. output load : v out = 5v figure 7 . load reg. vs. output load : v out = 5v 40 50 60 70 80 90 100 0.1 0.3 0.5 0.7 0.9 1.1 1.3 efficiency [%] output current [a] 11.6 11.7 11.8 11.9 12 12.1 12.2 12.3 12.4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 vout [v] output current[a] 85c 65c 25c 0c -25c -40c 40 45 50 55 60 65 70 75 80 85 90 0.1 0.3 0.5 0.7 0.9 1.1 1.3 efficiency [%] output current [a] 8.6 8.7 8.8 8.9 9.0 9.1 9.2 9.3 9.4 0.1 0.3 0.5 0.7 0.9 1.1 1.3 vout [v] output current[a] 85c 65c 25c 0c 40 45 50 55 60 65 70 75 80 85 90 0.1 0.3 0.5 0.7 0.9 1.1 efficiency [%] output current [a] 4.50 4.60 4.70 4.80 4.90 5.00 5.10 5.20 5.30 5.40 5.50 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 vout [v] output current[a] 85c 65c 25c 0c
p9221 - r datasheet ? 2017 integrated device technology, inc . 13 april 4 , 2017 figure 8 . rectifier voltage vs. load : v out = 12v figure 9 . rectifier voltage vs. load : v out = 9v figure 10 . rectif ier voltage vs. load : v out = 5v figure 11 . current limit vs. v il im figure 12 . x and y misa lignment figure 13 . max. p ower vs. misalignment : v out =12v 11.6 12 12.4 12.8 13.2 0.1 0.3 0.5 0.7 0.9 1.1 1.3 vrect [v] output current[a] 85c 65c 25c 0c -25c -40c 8.8 8.9 9.0 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 vrect [v] output current[a] 85c 65c 25c 0c 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 0.1 0.3 0.5 0.7 0.9 1.1 vrect [v] output current[a] 85c 65c 25c 0c 0 200 400 600 800 1000 1200 1400 1600 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ilim [ma] v ilim [v] 0 20 40 60 80 100 120 0 2 4 6 8 10 12 register values misalignment [mm] x-align y-align 0 2 4 6 8 10 12 14 16 18 50 60 70 80 90 100 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 output power [w] efficiency [%] misalignment [mm] efficiency output power
p9221 - r datasheet ? 2017 integrated device technology, inc . 14 april 4 , 2017 figure 14 . enable s tartup : v out = 12v; i out = 1.2a figure 15 . transient resp : v out = 12v; i out = 0 to 1.2a figure 16 . transient resp : v out = 12v; i out = 1.3 a to 0
p9221 - r datasheet ? 2017 integrated device technology, inc . 15 april 4 , 2017 7. function block diagram figure 17 . function al block diagram s y n c h r o n o u s r e c t i f i e r c o n t r o l b l o c k l d o v r e c t s i n k o v p 3 2 - b i t a r m p r o c e s s o r a s k m o d u l a t o r b s t 1 a c 1 a c 2 o u t v r e c t v o u t i s n s t s i l i m v o s e t r p p o r p p g v t d i e a d c m u x i 2 c s l a v e s c l s d a p e a k d e t e c t o r a n d l p f v d d 5 v l d o 5 v l d o 1 . 8 v v d d 1 8 g n d i s n s u v l o u v l o f s k d e m o d u l a t o r p h a s e d e t e c t o r a c 1 r s v x e n e n e n e n i n t b s t 2 c o m m 1 c o m m 2 a l i g n x a l i g n y d e n
p9221 - r datasheet ? 2017 integrated device technology, inc . 16 april 4 , 2017 8. theory of operation the p9221 - r is a highly - integrated, wireless power receiver targeted for 15 w applications . the device integrates a full - wave synchronous rectifier, low - dropout (ldo) linear regulator, and a 32 - bit arm ? - based m0 processor to manage all the digital control required to comply with the wpc - 1.2.2 communication protocol. the rectifier voltage and the output current are sampled periodically and digitized by the analog - to - digital converter ( adc ) . the digital equivalents of the voltage and current are supplied to the internal control logic, which de termines whether the loadin g conditions on the vrect pin indicate that a change in the operating point is required . if the load is heavy enough and brings the voltage at vrect below its target, the transmitter is set to a lower frequency that is closer to resonance and to a higher o utput power . if the voltage at vrect is higher than its target, the transmitter is instructed to increase its frequency . to maximize efficiency, the voltage at vrect is programmed to decrease as the ldos load current increases. the internal temperature is continuously monitored to ensure proper operation. in the event that the vrect voltage increases above 13.5 v, the control loop disables the ldo and sends error packets to the transmitter in an attempt to bring the rectifier voltage back to a safe operatin g voltage level while simultaneously clamping the incoming energy using the open - drain sink pin for vrect linear clamping. the clamp is released when the vrect voltage falls below the v ovp - dc minus v ovp - hys . see figure 17 . the receiver utilizes idts proprietary voltage clamping scheme , which limits the maximum voltage at the rectifier pin to 13.5v, reducing the voltage rating on the output capacitors while eliminating the need for over - voltage protection ( ovp ) capacitors. as a result, it provides a small application area, making it an i ndustry - leading wireless power receiver for high power den sity applications. combined with the p9242 - r transmitter, the p9221 - r is a complete wireless power system solution. 8.1 ldo C low dropout regulator s the p9221 - r has three low - dropout linear regulators . the main regulator is used to provide the power required by the battery charger where the output voltage can be set to either 9 v or 12 v . for more information about setting the output voltage , see section 8.2 . it is important to connect a minimum of 30f ceramic capacitance to the out pin. the other two regulators, vdd5v and vdd18 , are to bias the internal circuitry of the receiver . the ldos must have local 1f ceramic capacitors placed as close as possible to the pins . 8.2 setting the output voltage C voset t he output voltage on the p9221 - r is programmed by connecting the center tap of the external resistors r34 and r33 to the voset p in as shown in the application schematic in figure 24 . there are only two voltage s available : 9.0 v or 12v . t he recommended setting s for r33 and r34 are summarized in table 6 . the default output voltage is set to 12v in the p9221 - r e valuation b oard. for applications where the transmitter is capab le of delivering only 5w , the p9221 - r will automatically switch to 5v to ensure 5w power delivery. the 5w option can be disabled by adding r33 as described in table 6 . table 6 . setting the output voltage r34 (k ? ) r33 (k ? ) output voltage (v) 5v output o ption 10 open 12 enable 10 30 12 disable open 10 9 enable 10 3.3 9 disable
p9221 - r datasheet ? 2017 integrated device technology, inc . 17 april 4 , 2017 8.3 sink pin the p9221 - r has an internal automatic dc clamping to protect the device in the event of high voltage transient s . the vrect node must be connected to the s ink pin at all times using a 36 ? resistor with a greater than ? w rating . 8.4 rectifier voltage C vrect the p9221 - r uses a high \ efficiency synchronous rectifier to convert the ac signal from the coil to a dc signal on the v rect pin . during startup, the rectifier operates as a passive diode bridge. once the voltage on v rect exceeds t he under - voltage lock - out level ( uvlo ; see table 5 ) , the rectifier will switch into full synchronous bridge rectifier mode . a total capacitance of 30 f is recommended to minimize the output voltage ripple. 8.5 over - c urrent limit C ilim the p9221 - r has a programmable current limit function for protecting the device in the event of an over - current or short - circuit fault condition . when the output current exceeds the program m ed threshold , the p9221 - r will limit the load current by reducing the output voltage . the current limit should be set to 130% of the target maximum output current . see the ilim pin description in table 1 for further information . 8.6 interrupt function C int ? ? ? ? ? ? the p9221 - r provides an open - drain, active - low interrupt output pin. it is asserted low when en is high or any of the following fault conditi ons have been triggered: the die temperature exceeds 140c, the external thermistor measurement exceeds the threshold (see section 8.9 ) , or an over - current (oc) or over - voltage (ov) condition is detected . during normal operation, the int pin is pulled high . this pin can be connected to the interrupt pin of a microcontroller. the source of the trigger for the interrupt is available in the i 2 c interrupt register (see table 12 ) . 8.7 enable pin C en ? ? ? ? ? the p9221 - r can be disabled by applying a logic high to the en pin. when the en pin is pulled high , the device is in s hut d own mode . connect ing the enable pin to logic low activate s the device. 8.8 thermal protection the p9221 - r integrates thermal shutdown circuitry to prevent damage resulting from excessive thermal stress that may be encountered under fault conditions. this circuitry will shut down or reset the p9221 - r if the die temperature exceeds 140c. 8.9 external temperature sensing C ts the p9221 - r has a temperature sensor input , t s , which can be used to monitor an external temperature by using a thermisto r. the built - in comparator s r eference voltage was chosen to be 0.6 v in the p9221 - r , and it is used for monitoring the voltage level on the ts pin as described by equation 1 . v ts = v vdd18 ntc r+ntc equation 1 where ntc is the thermistor s resistance and r is the pull - up r esistor connected to vdd18 pin . the over C temperature shutdown is tr igged when the ts pin voltage is lower than 0.6v ; for more information , see figure 24 .
p9221 - r datasheet ? 2017 integrated device technology, inc . 18 april 4 , 2017 8.10 alignment guide C al i gnx and al i g ny this feature is used to provide directional information regarding the transmit coil and receive coil alignment while the wireless charger is in normal ope ration mode. sensing coils (see the basic application circuit on the first page) are placed on the wireless power receiver side between the power rx coil and power tx coil. special design enables the sensing coils to output zero voltage wh en the alignment is optimum while misalignment between the transmitter and receiver coils will result in a voltage on the sensing coils . t hese signals are internally rectified, filtered , and passed through the adc providing quantitative information on the amount of misalig nment . the higher the signal is , the more the coils are misalig ned . furthermore, the signal magnitude on al i g nx and al i g ny provides direction al information by measuring the phase between the input power ac signal and horizontal and vertical alignment signals . once the signal pass es through the adc, the alignment info rmation is represented by two 8 - bit signed numbers , which can be read from the alignment x value and alignment y value i 2 c register s defined in table 21 and table 22 respectively, which indicate the misalignment direction and magnitude . the a pplication processor can provide 2d visual graphic s that suggest how much the power coils are misaligned in each direction and can suggest that the user move the device on the tx pad for the best alignment to improve the power transferred and reduce the charging time. 8.11 received power packet offset and gain calibration C rppo and rppg the received power packet offset (rppo) and received power packet gain (rppg) calibration s have dedicated pin s for tuning foreign object detection ( fod ) . the offset calib ration can be tuned by the voltage level of rppo to a value between 0.1v to 2.1 v , which corresponds to a power offset range of 1.54w to 2.34w. the gain can be modified by setting the voltage level of the rppg pin. the range of the control gain is from 0.12 2 to 2.33 where the level is determined by a ratio metric voltage in the range of 0.1v to 2.1v on the rppg pin. to disable the fod, the voltage on both rppo and rppg must be set to 0.1v. neither pin should be floating . if fod is not required , the rppg and rppo must be set to 0.9v , which defaults to g ain = 1 and o ffset = 0. 8.12 advanced foreign object detection (fod) when metallic objects are exposed to an alternating magnetic field, eddy currents cause such objects to heat up. examples of such parasitic metal objects are coins, keys, paper clips, etc. the amount of heating depends on the strength of the coupled magnetic field, as well as on the characteristics of the object, such as its resistivity, size, and shape. in a wireless power transfer system, the heating manifests itself as a power loss, and therefore a reduction in power - transfer efficiency. moreover, if no appropriate measures are taken, the heating could be sufficient that the for eign object could become heated to an undesirable temp erature. during the p ower t ransfer phase, the receiver periodically will communicate to the transmitter the amount of power received by means of a r eceived p ower packet. the transmitter will compare this power with the amount of power transmitted during th e same time period. if there is a significant unexplained loss of power, then the transmitter will shut off power delivery because a possible foreign object m ight be absorbing too much energy. for a wpc system to perform this function with sufficient accur acy, both the transmitter and receiver must account for and compensate for all of their known losses. such losses could be due to resistive losses or nearby metals that are part of the transmitter or receiver, etc. because the system accurately measures it s power and accounts for all known losses, it can thereby detect foreign objects because they cause an unknown loss. the wpc spec ification requires that a power receiver must report to the power transmitter its received power (p pr ) in a r eceived - p ower p acket (rpp) . the maximum value of the r eceived p ower accuracy ? depends on the m aximum p ower of the p ower r eceiver as defined in table 7 . the power receiver must determine its p pr with an accuracy of ? , and report its received power as p received = p pr + ? . this means that the reported received power is always greater than or equal to the transmitted power (p pt ) if there is no f oreign o bject (fo) present on the interface surface.
p9221 - r datasheet ? 2017 integrated device technology, inc . 19 april 4 , 2017 table 7 . maximum estimated power loss maximum power [w] maximum ?? [mw] 15 750 the compensation algorithm includes values that are programmable via either the i 2 c interface or otp ( one - time programm able) bits. programmability is necessary so that the calibration settings can be optimized to match the power transfer characteristics of each particular wpc system to include the power losses of the transmit and receive coils, battery, sh ielding , and case materials under no - l oad to full - load conditions. the values are based on the comparison of the received power against a reference power curve so that any foreign object can be sensed when the received power is different than the expected system power.
p9221 - r datasheet ? 2017 integrated device technology, inc . 20 april 4 , 2017 9. communication interface 9.1 modulation/communication the wireless medium power charging system uses two - way communication : receiver - to - transmi tter and transmitter - to receiver. receiver - to - transmitter communication is accomplished by modulating th e load seen by the receiver's inductor ; the communication is purely digital and symbols 1s and 0s ride on top of the power signal that exists between the two coils. modulation is done with am plitude - shift keying (ask) modulation using internal switches t o connect external capacitors from ac1 and ac2 to ground ( s ee figure 17 ) with a bit rate of 2kbps. to the transmitter, this appears as an impedance cha nge, which results in measurable variations of the transmitters output waveform. the power transmitter detects this as a modulation of coil current/voltage to receive the packets. transmitt er - to - receiver communication is accomplished by frequency - shift keying (fsk) modulation over the power signal frequency. the power receiver p9221 - r has the means to demodulate fsk data from the power signal frequency and use it in order to establish the handshak ing protocol with the power transmitter. the p9221 - r implements fsk communication wh en used in conjunction with wpc - compliant transmitters , such as the p9242 - r . the fsk communication protocol allows the transmitter to send data to the receiver using the po wer transfer link in the form of modulating the power transfer signal . this modulation appear s in the form of a change in the base operating frequency ( f op ) to the modulated operating frequency ( f mod ) in periods of 256 consecutive cycles . equation 2 should be used to compute the modulated frequency based on any given operating frequency. the p9221 - r will only implement positive fsk p olarity adjustments ; in other words, the modulated frequency will always be higher than the operating frequency during fsk communication. communication packets are transmitted from transmitter to receiver with less than 1% positive frequency deviation following any receiver - to - transmitter communication packet. the frequency deviation is calculated using equation 2 . f mod = 60000 60000 f op ? 3 [khz] equation 2 where f mod is the changed frequency in the power signal frequency ; f op is the base operating frequency of the power transfer; and 60 000 k hz is the internal oscillator responsible for counting the period of the power transfer signal. the fsk byte - encoding scheme and packet structure compl y with the wpc specification revision 1.2.2 . the fsk communication uses a bi - phase encoding scheme to modulate data bits into the power transfer signal. the start bit will consist of 512 consecutive f mod cycles (or logic 0) . a logic 1 value will be sent by sending 256 consecutive f op cycles followed by 256 f mod cycles or vice v ersa, and a logic 0 is sent by sending 512 consecutive f mod or f op cycles. figure 18 . example of differential bi - phase de coding for fsk each byte will comply with the start, data, parity , and stop asynchronous serial format structure shown in figure 19 : figure 19 . example of asynchronous serial byte format for f sk t c l k = 2 5 6 / f o p o n e z e r o o n e z e r o o n e o n e z e r o z e r o 5 1 2 c y c l e s 2 5 6 c y c l e s start stop parity b 0 1 2 3 4 5 6 7 b b b b b b b
p9221 - r datasheet ? 2017 integrated device technology, inc . 21 april 4 , 2017 9.2 bit en coding scheme for ask as required by the wpc, the p9221 - r uses a differential bi - phase encoding scheme to modulate data bits onto the power signal. a clock frequency of 2khz is used for this purpose. a logic one bit is encoded using two narrow transitions, whereas a logic zero bit is encoded using one wider transition as shown below: figure 20 . bit en coding s cheme 9.3 byte en coding for ask each byte in the communication packet comprises 11 bits in an asynchronous serial format, as shown in figure 21 . figure 21 . byte en coding scheme each byte has a start bit, 8 data bits, a parity bit, and a single stop bit. 9.4 packet structure the p9221 - r communicates with the base station via communication packets. each communication packet has the following structure: figure 22 . communication packet structure preamble header message checksum t clk one zero one zero one one zero zero s t a r t s t o p p a r i t y b 0 1 2 3 4 5 6 7 b b b b b b b
p9221 - r datasheet ? 2017 integrated device technology, inc . 22 april 4 , 2017 10. wpc mode characteristics the extended power profile adds a negotiation phase, a calibration phase, and renegotiation phase to the basic system control functionality of the base line power profile, as shown in figure 23 . figure 23 . wpc power transfer phases flowchart 10.1 selection phase or startup in the selection pha se, the power tran smitter determines if it will proceed to the ping phase after detecting the placement of an object. in this phase, the power transmitte r typically monitors th e interface surfac e for the placement and removal of objects using a small measurement s ignal. this measurement signal should not wake u p a power receiver that is positioned on the interface surface. 10.2 ping phase (digital ping) in the ping phase, t he power transmitter will transmit power and will detect the response from a possible power receiv er. this response ensures the power transmitter that it is dealing with a power receiver rather than some unknown object. when a mobile device containi ng the p922 1 - r is placed on a wpc qi charging pad, it responds to the application of a power signal by rectifying this power signal . when the voltage on vrect is greater than the uvlo threshold, then the internal bandgaps, reference voltage , and the internal voltage regulators (5v and 1.8 v) are turned on , and microcontrollers startup is initiated enabling the wpc communication protocol. if the power transmitter correctly receive s a signal strength pack et, the power transmitter proceeds to the identification and configuration phase of the power transfer, maintaining the power signal output. s t a r t o b j e c t d e t e c t e d e r r o r c o n d i t i o n n e g o t i a t i o n f a i l u r e o r e r r o r c o n d i t i o n o r f o d c a l i b r a t i o n s u c c e s s f u l n e g o t i a t i o n s u c c e s s f u l n e g o t i a t i o n r e q u e s t e d n o n e g o t i a t i o n r e q u e s t e d ( < = 5 w p o w e r r e c e i v e d o n l y ) r e n e g o t i a t i o n c o m p l e t e d c a l i b r a t i o n f a i l u r e o r e r r o r c o n d i t i o n n o r e s p o n s e o r n o p o w e r n e e d e d s e l e c t i o n p i n g i d e n t i f i c a t i o n a n d c o n f i g u r a t i o n n e g o t i a t i o n r e n e g o t i a t i o n c a l i b r a t i o n p o w e r t r a n s f e r p o w e r r e c e i v e r p r e s e n t p o w e r t r a n s f e r c o m p l e t e o r e r r o r c o n d i t i o n r e n e g o t i a t i o n r e q u e s t e d e r r o r c o n d i t i o n
p9221 - r datasheet ? 2017 integrated device technology, inc . 23 april 4 , 2017 10.3 identification an d configuration phase the identification and configuration phase is the part of the protocol t hat the power transmitter exe cutes in order to ident ify the power receiver and es tablish a defa ult power transfer contr act. this protocol extend s the digital ping in order to enable the power receiver to communicate the relevant information. in this p hase, the power receiver identifies itself and provides information for a default power transfer contract: ? it sends the configuration packet . ? if the power transmitter does not ackn owledge the request (does not transmit fsk modulation), the power receiver will assume 5w output power. 10.4 negotiation phase i n th e negotiation phase , the p ower r eceiver negotiates changes to the default power transfer con tract. in addition, t he power receiver verifies that the power transmitter has not detected a foreign object. 10.5 calibration phase in th e calibration phase , the power receiver provides information that the power transmitter can use to improve its ability to detect foreign object s during power transfer. 10.6 power transfer phase in this phase, the p9221 - r controls the power transfer by means of the follow ing control data pac kets: ? control error packets ? received power packet (rpp, fod related) ? end power transfer (ept) packet once the i dentification and configuration phase is completed, the transmitter initiates the power transfer mode . the p9221 - r control circuit measures the rectifier voltage and sends error packets to the transmitter to adjust the rectifier voltage to the level requi red to maximize the efficiency of the linear regulator and to send to the transmitter the actual received power packet for foreign object detecti on (fod) to guarantee safe , efficient power transfer. in the event of an ept issued by the application, the p92 21 - r turns off the ldo and continuously send s ept packets until the transmitter removes the power and the rectified voltage on the receiver side drops below the uvlo threshold.
p9221 - r datasheet ? 2017 integrated device technology, inc . 24 april 4 , 2017 11. functional registers the following tables provide the address locations, field names, available operations (r or rw), default values , and functional descriptions of all the internally accessible registers contained within the p9221 - r . the default i 2 c slave address is 6 1 hex . table 8 . device identification register address and bit register field name r/w default function and description 00 hex [7:0] part_number _l r 2 0 hex chip id low byte 01 hex [7:0] part_number _h r 92 hex chip id high byte table 9 . firmware major revision address and bit register field name r/w default function and description 04 hex [7:0] fw_major_rev_l r 0 1 hex major firmware revision low byte 05 hex [7:0] fw_major_rev_h r 00 hex major firmware revision high byte table 10 . firmware minor revision address and bit register field name r/w default function and description 06 hex [7:0] fw_minor_rev_l r 2 6 hex minor firmware revision low byte 07 hex [7:0] fw_minor_rev_h r 0 4 hex minor firmware revision high byte table 11 . status registers address and bit register field name r/w default function and description 34 hex [7] vout_status r 0 bin 0 output voltage is off . 1 output voltage is on . 34 hex [6] reserved r 0 bin 34 hex [5] reserved r 0 bin 34 hex [4] reserved r 0 bin 34 hex [3] reserved r 0 bin 34 hex [2] thermal_shtdn_status r 0 bin 0 indicates no over - temperature condition exists. 1 indicates that die temperature exceeds 130c or ntc is less than 0.6v . the p9221 - r sends an end power transfer ( ept ) packet to the transmitter . 34 hex [1] vrect_ov_ status r 0 bin 1 indicates rectifier exceeds 20v for v out =12. ept packet send. 34 hex [0] current_limit_status r 0 bin 1 indicates current limit has been exceeded. the p9221 - r sends an end power transfer (ept) packet to the transmitter. 35 hex [7 :0 ] reserved r 0 0 hex
p9221 - r datasheet ? 2017 integrated device technology, inc . 25 april 4 , 2017 table 12 . interrupt status register s address and bit register field name r/w default function and description 36 hex [7] int_ vout_status r 0 bin 0 output voltage has not changed. 1 output voltage changed. 36 hex [6] reserved r 0 bin 36 hex [5] reserved r 0 bin 36 hex [4] reserved r 0 bin 36 hex [3] reserved r 0 bin 36 hex [2] int_over_temp_status r 0 bin 1 indicates over - temperature condition exists. 36 hex [1] int_vrect_ov_ status r 0 bin 1 indicates rectifier over - v oltage condition exists. 36 hex [0] int_ oc _limit_status r 0 1 indicates current limit has been exceeded. 37 hex [7:0] reserved r 0 0 hex note: i f any bit in the interrupt status register 36 hex is 1 and the corresponding bit in the interrupt enable register 38 hex is set to 1, the int pin will be pulled down indicat ing an interrupt event has occurred . table 13 . interrupt enable registers address and bit register field name r/w default function and description 38 hex [7] vout_chgn_intr_en rw 0 bin 0 disable s the interrupt. "1" enable s the interrupt. 38 hex [6] reserved r 0 bin 38 hex [5] reserved r 0 bin 38 hex [4] reserved r 1 bin 38 hex [3] reserved r 0 bin 38 hex [2] over_temp_int_en r 0 bin 0 disables the interrupt. "1" enables the interrupt. 38 hex [1] vrect_ov_int_en rw 0 bin 0 disable s the interrupt. "1" enable s the interrupt. 38 hex [0] oc_limit_int_en rw 0 bin 0 disable s the interrupt. "1" enable s the interrupt. 39 hex [7:0] reserved rw 00 hex table 14 . battery charge status address and bit register field name r/w default function and description 3a hex [7:0] batt_charg_ status r/w 0 0 hex battery charge status value sent to transmitter. [a] [a] firmware only forwards the data fro m the application processor to transmitter.
p9221 - r datasheet ? 2017 integrated device technology, inc . 26 april 4 , 2017 table 15 . end power transfer the application processor initiates the end power transfer (ept). address and bit register field name r/w default function and description 3b hex [7:0] ept_code r/w 0 0 hex ept_code sent to transmitter. table 16 . read register C output voltage vout= adc_vout ? 6 ? 2.1 4095 address and bit register field name r/w default function and description 3c hex [7:0] adc_ vout [7:0] r 00 hex 8 lsb of v out adc value . 3d hex [7:4] reserved r 0 hex reserved . 3d hex [3:0] adc_v out [11:8] r 0 hex 4 msb of v out adc value. table 17 . read register C vrect voltage vrect = adc_vrect ? 10 ? 2.1 4095 address and b it register field name r/w default function and description 40 hex [7:0] adc_ vrect [7:0] r C 8 lsb of vrect adc value. 41 hex [7:4] reserved r 0 hex reserved 41 hex [3:0] adc_ vrect [11:8] r C 4 msb of vrect adc value. table 1 8 . read register C iout c urrent iout= rx_iout ? 2 ? 2.1 4095 address and b it register field name r/w default function and description 44 hex [7:0] rx_i out [7:0] r hex C 8 ls b of i out . output current in ma. 45 hex [7:0] rx_i out [15:8] r hex C 8 msb of i out. output current in ma
p9221 - r datasheet ? 2017 integrated device technology, inc . 27 april 4 , 2017 table 19 . read register C die temperature t die = ( adc_die_temp ? 1350 ) 83 444 C 273 where adc_die_temp = 12 bits from adc_die_temp_h and adc_die_temp_l. address and bit register field name r/w default function and description 46 hex [7:0] adc_die_temp_l r - 8 lsb of curren t die temperature in c. 47 hex [7:4] reserved r 0 hex reserved 47 hex [3:0] adc_die_temp_h r - 4 msb of curren t die temperature in c. table 20 . read register C operating frequency f op = 64 ? 6000 op_freq [15:0] address and bit register field name r/w default function and description 48 hex [7:0] o p _f req [7:0] r - 8 lsb ac signal frequency on the coil . 49 hex [7:0] o p _f req [15:8] r - 8 msb ac signal frequency on the coil. table 21 . alignment x value registe r note: valid only in presence of the alignment pcb coil. (see section 8.10 or the p9221 - r evaluation kit u ser m anual for more information.) address and bit register field name r/w default function and description 4b hex [7:0] align_x r - 8 - bit signed integer representing alignment between tx and rx coil in the x - direction . the value is application - specific. table 22 . alignment y value register note: valid only in presence of the alignment pcb coil. (see section 8.10 or the p9221 - r evaluation kit user manual for more information.) address and bit register field name r/w default function and description 4c hex [7:0] align_y r - 8 - bit signed integer representing alig nment between tx and rx coil in the y - direction . the value is application - specific.
p9221 - r datasheet ? 2017 integrated device technology, inc . 28 april 4 , 2017 table 23 . command register address and bit register field name r/w default function and description 4e hex [7:6] reserved r 0 hex reserved . 4e hex [5] clear interrupt rw 0 hex if application processor sets this bit to "1 , " the p922 1 - r clears the interrupt pin . 4e hex [4] reserved r 0 hex reserved 4e hex [3] send end of power rw 0 hex if application processor sets this bit to "1 , " the p922 1 - r sends the end power transfer packet (defined in the end of power transfer r egister shown in table 15 ) to the transmitter and then sets this bit to "0 ." 4e hex [2] reserved r 0 hex reserved 4e hex [1] toggle ldo on/off rw 0 hex if application processor sets this bit to "1 , the p922 1 - r toggles the ldo output once (from on to off or from off to on), and then sets this bit to 0 . 4e hex [0] reserved r 0 hex reserved
p9221 - r datasheet ? 2017 integrated device technology, inc . 29 april 4 , 2017 12. application information 12.1 power dissipation and thermal requirements the use of integrated circuits in low - profile and fine - pitch surface - mount packages requires special attention to power dissipation. many system - dependent issues such as thermal coupling, airflow, added heat sinks, convection surfaces, and the presence of other heat - generating components. the p9221 - r package has a maximum power dissipation of approximately 1.72w , which is governed by the number of thermal vias between the package and the printed circuit board. the die s maximum power dissipation is specifie d by the junction temperature and the package thermal resistance. the wlcsp package has a typical ja of 47 o c/w with 8 thermal vias and 77 o c/w with no thermal vias. maximizing the thermal vias is highly recommended. the ambient temperature surrounding the power ic will also have an effect on the thermal limits of the pcb design. the main factors influencing thermal resistance ( ja ) are the pcb characteristics and thermal vias. for example, in a typical still - air environment, a significant amount of the heat generated is absorbed by the pcb. changing the design or configuration of the pcb changes the overall thermal resistivity and therefore the boards heat - sinking efficiency. three basic approaches for enhancing thermal performance are listed below: ? improv ing the power dissipation capability of the pcb design and i mproving the thermal coupling of the component to the pcb. ? introducing airflow into the system. first, the maximum power dissipation for a given situation should be calculated using equation 3 : p d(max) = ( t j(max) ? t a ) ja equation 3 where p d(max) = maximum power dissipation ja = package thermal resistance (c/w) t j(max) = maximum device junction temperature (c) t a = ambient temperature (c) the maximum recommended junction temperature (t j(max) ) for the p9221 - r device is 125c. the thermal resistance of the 52 - wlcsp package (ahg52) is nominally ja =47c/w with 8 th ermal vias. operation is specified to a maximum steady - state ambient temperature (t a ) of 85c. therefore, the maximum recommended power dissipation is p d(max) = (125c - 85c) / 47c/w ? 0.85 watt all the above - mentioned thermal resistances are the values found when the p9221 - r is mounted on a standard board of the dimensions and characteristics specified by the jedec 51 standard. 12.2 recommended coils the following coil is recommended with the p9221 - r receiver for 15w applications for optimum performance. the recommended vendor has been tested and verified. table 24 . recommended coil manufacture r s output power vendor part number inductance at 100khz acr at 20c 15w amotech asc - 504060 e00 - s00 8.2h 220 m ?
p9221 - r datasheet ? 2017 integrated device technology, inc . 30 april 4 , 2017 12.3 typical application schematic figure 24 . p9221 - r typical application schematic d1 led c12 np c10 10uf int int c9 3.3nf r18 np vdd5v d6 5.1v r8 0 c25 np algx r33 np r39 10k c19 0.1uf (sda) int c21 10uf c16 15nf u1 p9221-r comm1 a1 comm2 a6 rsv4 b1 rsv5 b6 en b5 alignx a2 scl a3 voset a4 rppg a5 sda b3 aligny b2 ilim b4 rppo c4 den c5 out d1 int c3 sink c2 out d2 out d3 out d4 out d5 out d6 vrect e1 vrect e2 vrect e5 vrect e6 vrect f2 vrect f3 vrect f4 vrect f5 ac1 g2 ac1 h1 ac1 h2 ac2 g5 ac2 h5 ac2 h6 bst1 g1 bst2 g6 gnd c1 gnd c6 gnd j1 gnd j2 gnd j3 gnd j4 gnd j5 gnd j6 vdd5v f1 vdd18 f6 rsv3 g3 rsv2 h3 rsv1 g4 ts h4 c20 1uf r19 10k /en i2crail vout voset p9221-r mm ev board v2.1 c31 0.1uf c8 15nf vrect r35 0 j1 i2c 1 2 3 4 5 l1 scl r17 10k vpp18 vdd5v r30 10k r22 np r2 36 r14 5.1k c3 100nf/50v rpo c11 10uf r13 5.1k thm c23 0.1uf gnd1 r28 10k r16 10k vrect r29 10k (scl) c7 np vosns ilim r34 10k r23 10k c22 10uf vdd5v r38 10k rx power coil alignx coil c18 1uf c6 47nf vpp18 vrect r1 5.1k algy thm c2 100nf/50v d7 5.1v u2 np a0 1 a1 2 a2 3 vss 4 sda 5 scl 6 wp 7 vcc 8 e_pad 9 vpp18 rts np vpp18 c1 100nf/50v aligny coil wp c5 100nf/50v lc sda r27 10k od3 c33 10uf vout den ac2t ts c15 np gnd r6 np r15 10k od4 gcom ac2 rpg c14 47nf
p9221 - r datasheet ? 2017 integrated device technology, inc . 31 april 4 , 2017 12.4 bill of materials (bom) table 25 . p9221 - r mm evaluation kit v2.1 bill of materials item reference quantity value description part number pcb footprint 1 ac2t, vdd5v, vpp18, voset, ts, sda, scl, rpo, rpg, int, ilim, gcom, den, algy, algx, /en 16 pth_tp test pad 10mil_35pad 2 ac2, lc 2 np t est point test_pt_sm_135x70 3 c1, c2, c3, c5 4 100nf/5 0v cap cer 0.1uf 50v x5r 0402 grm155r61h104ke19d 402 4 c6, c14 2 47nf cap cer 0.047uf 50v x7r 0402 c1005x7r1h473k050bb 402 5 c7, c15 2 np cap cer 0.047uf 50v x7r 0402 c1005x7r1h473k050bb 402 6 c8, c16 2 15nf cap cer 0.015uf 50v x7r 0402 GRM155R71H153KA12J 402 7 c9 1 3.3nf cap cer 3300pf 50v x7r 0402 cl05b332kb5nnnc 402 8 c10, c11, c21, c22, c33 5 10uf cap cer 10uf 25v x5r 0603 cl10a106ma8nrnc 603 9 c12 1 np cap cer 10uf 25v x5r 0603 cl10a106ma8nrnc 603 10 c18 1 np cap cer 1uf 10v x5r 0402 grm155r61a105ke15d 402 11 c20 1 1uf cap cer 1uf 10v x5r 0402 grm155r61a105ke15d 402 12 c19, c25, c31 3 0.1uf cap cer 0.1uf 10v x5r 0201 c0603x5r1a104k030bc 201 13 c23 1 0.1uf cap cer 0.1uf 25v x5r 0201 cl03a104ka3nnnc 201 14 d1 1 led led green clear 0603 smd 150060gs75000 0603_diode 15 d6,d7 2 5.1v diode zener 5.1v 100mw 0201 czrz5v1b - hf 201 16 gnd1, vrect, vout, vosns, gnd 5 test point test point pc miniature smt 5015 test_pt_sm_135x70 17 l1 1 rx coil amotech, rx power coil asc - 504060 e00 - s00 10mil_35pad 18 j1 1 np header_1x5_0p1pitch60p42d 68002 - 205hlf header_1x5_0p1pitch60p42d 19 rts 1 np ntc2 20 r1, r13, r14 3 5.1k res smd 5.1k ohm 5% 1/16w 0402 mcr01mrtj512 402 21 r2 1 36 res smd 36 ohm 5% 1/2w 0805 erj - p06j360v 805 22 r6 1 np res smd 0.0ohm 1/10w 0402 erj - 2ge0r00x 402 23 r8 1 0 res smd 0.0ohm 1/10w 0402 erj - 2ge0r00x 402 24 r15, r16 2 10k res smd 10kohm 1% 1/10w 0603 rc0603fr - 0710kl 603 25 r17, r19, r23, r27, r28, r29, r30, r34, r38, r39 10 10k res smd 10k ohm 5% 1/10w 0402 erj - 2gej103x 402 26 r18, r22, ,r33 3 np res smd 10k ohm 5% 1/10w 0402 erj - 2gej103x 402 27 r35 1 0 res smd 0.0ohm jumper 1/10w 0603 mcr03ezpj000 603 28 u1 1 p9221 - r wireless power receiver p9221 - r csp52_2p64x3p94_0p4mm 29 u2 1 np ic eeprom 128kbit 400khz 8tdfn 24aa128t - i/mny tdfn08
p9221 - r datasheet ? 2017 integrated device technology, inc . 32 april 4 , 2017 13. package drawings figure 25 . package outline drawing
p9221 - r datasheet ? 2017 integrated device technology, inc . 33 april 4 , 2017 14. recommended land pattern figure 26 . ahg52 52 - wlcsp land pa ttern
p9221 - r datasheet ? 2017 integrated device technology, inc . 34 april 4 , 2017 15. special notes: ahg52 wlcsp - 52 package assembly unopened dry packaged parts have a one - year shelf life. the hic indicator card for newly - opened dry packaged parts should be checked. if there is any moisture content, the parts must be baked for a minimum of 8 hours at 125?c within 24 hours of the assembly reflow process. 16. marking diagram 1. line 1 company name . 2. truncated part number . 3. y y ww is the last digit of the year and week that the part was assembled. ** is the lot sequential code. 4. $ denotes mark code , - r is part of the device part number 17. ordering information orderable part number description and package msl rating shipping packaging ambient temperature p9221 - rahgi8 p9221 - r wireless power receiver for 15w applications, 2.64 ? 3.94 mm 52 - wlcsp (ahg52) msl1 tape and reel 0c to +85c p9221 - r - evk p9221 - r - evk evaluation board i d t p 9 2 2 1 y y w w * * $ - r
p9221 - r datasheet ? 2017 integrated device technology, inc . 35 april 4 , 2017 18. revision history revision date description of change april 4 , 2017 ? update to wpc - 1.2.3 compliant ? update for i 2 c slave address = 61 hex ? update for device identification register ? update for firmware revision number register ? update s for table 13 and table 16 . ? update for recommended coil part number and related entry in bom . ? update for disclaimer ? addition of r9221 - r evaluation kit order code ? minor edits december 1 6 , 2016 preliminary release. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 284 - 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) and its affiliated companies (herein referred to as idt) reserve the ri ght to modify the products and/or specifications described herein at any time, without notice, at idt's sole discretion. performanc e specifications and operating parameters of the described products are determined in an independent state and are not guaran teed to perform the same way when installed in customer products. the information contained herein is provided without representati on or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt's products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life suppor t systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, wri tten agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. fo r datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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